Power & Delay Analysis of D Flip Flop using MTCMOS Technique

This paper enumerates low power, high speed design of TSPC (True Single Phase Clocking) D flip-flop having less number of transistors. This technique allows circuit to achieve lowest power consumption with minimum transistor count. Design of low power device is now an essential field of research due to increase in demand of portable devices. In the circuit as the scaling increase the leakage powers increases. There are various technique to reduce the leakage current in which MTCMOS (Multi threshold CMOS) is one of the best technique to reduces leakage current is known as power gating. Power gating method is used to optimize power and delay in the circuits. In this paper a single edge triggered D flip flop with low power and low area requirements is proposed. This D flip flop has been implemented using 180 nm technology.